The invention relates generally to the design and fabrication of semiconductor devices, such as integrated circuit (IC) chips and, more particularly, to the steps involved in taking a “real chip design” and ensuring that the design is physically feasible, correcting the implementation based on process limitations, if necessary.
Computer-Aided Design (CAD)
Recently, various excellent CAD (Computer Aided Design) tools using computer technology have been developed. These CAD tools are now used to carry out almost all required operations in developing semiconductor integrated circuits, such as logic designing and layout designing.
FIG. 1A illustrates a “generic” Computer-Aided Design (CAD) system 100, comprising a calculating unit (computer, workstation) 102, a database 104 for storing a design library and/or design rules, an input device 106 such as a mouse or a tablet, a keyboard 108 for entering textual or numeric data, a display device 110 such as a computer monitor, a printout device 112 such as a printer, an output device 114 for storing designs and data on computer-readable medium such as flash drive or optical disc, and an interface 116 to a network 118 such as a local area network or the Internet for interacting with other users, interconnected as illustrated.
Some design elements of an integrated circuit (IC) are relatively more complex than others. A line, for example, is a relatively simple design element. A single transistor involves a combination of fundamental design elements. A static random access memory (SRAM) cell is an example of a yet more complex design. Examples of simple and complex designs are presented and discussed hereinbelow, with respect to FIGS. 1C-1F.
SRAM
Static random access memory (SRAM) is a type of semiconductor memory where the word “static” indicates that it, unlike “dynamic” RAM (DRAM), does not need to be periodically refreshed, as SRAM uses bistable latching circuitry to store each bit. However, SRAM is still volatile in the (conventional) sense that data is lost when powered down.
Random access means that locations in the memory can be written to or read from in any order, regardless of the memory location that was last accessed.
Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit.
FIG. 1B illustrates, schematically, a typical SRAM cell design, having 6 transistors, interconnected as shown. In order to implement the design, various physical elements need to be fabricated, such as field effect transistors (FETs) having gates, diffusion regions, contact structures, and the like, each of which is generally manufactured in a given one or more steps in a sequence of many steps.
U.S. Pat. No. 6,380,024, incorporated by reference herein, discloses a SRAM cell, similar to that of FIG. 1B, and also illustrates an exemplary physical implementation corresponding to a schematic design for the cell.
Photolithography
Photolithography (or optical lithography) is a process used in semiconductor fabrication to selectively remove parts of a thin film (or the bulk of a substrate). Generally, it uses light to transfer a geometric pattern from a photomask to a light-sensitive chemical (photoresist, or simply “resist”) on the substrate. A series of chemical treatments then engraves the exposure pattern into the material underneath the photoresist. In a complex integrated circuit (for example, modern CMOS), a wafer may go through the photolithographic cycle up to 50 times, or more.
Photolithography resembles the conventional lithography used in printing, and shares some fundamental principles with photography. It is used because it affords control over the shape and size of the objects it creates, and because it can create patterns over an entire surface simultaneously. Its main disadvantages are that it requires a flat substrate to start with, it is not very effective at creating shapes that are not flat, and it can require extremely clean operating conditions. Also, at extremely small dimensions comparable to the wavelength of light itself, photolithography has some inherent limitations which need to be accommodated or compensated for.
As used herein, “photolithography” may include using electromagnetic radiation having wavelengths shorter than those of light, such as X-rays. A nanometer (nm) is one-billionth of a meter. The wavelengths of visible light, which is one form of electromagnetic radiation, ranges from approximately 700 nm (red light) to 400 nm (violet light). Ultraviolet radiation has a wavelength of approximately 100 nm. Modern semiconductor devices have features that are (for example) only 50 nm, which is already much smaller than the shortest visible light wavelength. X-rays have a wavelength of approximately 1 nm. Radio, television and microwave radiation has wavelengths that are longer than that of visible light, such as centimeters (cm) or meters, and are thus generally not of interest for photolithography. (However, radio frequency (RF) energy may be used, for example, in generating plasmas for etching semiconductor devices.)
Manufacturing semiconductor devices and elements having sizes smaller than one wavelength of light embraces a technology called “sub-resolution lithography”. A key element of sub-resolution technology is using a technique Optical Proximity Correction (OPC).
Optical Proximity Correction (OPC)
As the level of integration in an integrated circuit (IC) continues to increase, dimensions of each circuit device are reduced correspondingly. Photolithography is an important step in the fabrication of semiconductors. Photolithography is involved in processes related to the fabrication of metal-oxide-semiconductor (MOS) devices such as the patterning thin films such as gate conductors (PC) and the marking out of active areas (RX) for implanting dopants. To attain higher level of integration, a few methods capable of increasing mask resolution has been suggested. One such method is optical proximity correction (OPC).
Generally, the idea behind optical proximity correction is the eliminate line offset due to proximity effect. Proximity effect refers to the phenomenon that occurs when a beam of light shines through an optical mask and projects onto a wafer. Due to diffraction of light beam on passing a material medium, the light beam will expand out somewhat. Furthermore, some of the light may pass through the photoresist layer into the wafer and then reflect back from the semiconductor substrate leading to interference. Hence, some portion of the photoresist may be double-exposed. The seriousness of such occurrences is intensified when the feature line width of an integrated circuit is small, especially when the wavelength of the light source approaches the width of a line pattern.
An integrated circuit (IC) chip typically begins its life as a design, referred to as a “real chip design”. The various lines and shapes of circuit elements are designed on a computer, resulting in an overall pattern. Then, an optical mask may be made and used to transfer the computer-generated design to a layer of material, such as photoresist, on the wafer. The design is substantially replicated in the layer of material (photoresist). Then, a process such as etching may be performed to create patterns replicating the design in a layer of material (such as polysilicon, or oxide, or nitride) which is under the photoresist.
Optical proximity correction (OPC) is a technique used to modify real chip designs, so as to render them manufacturable. OPC is a photolithography enhancement technique commonly used to compensate for image errors due to diffraction or process effects. The two most common applications for OPC are linewidth differences between features in regions of different density (e.g., center vs. edge of an array, or nested vs. isolated lines), and line end shortening (e.g., gate overlap on field oxide). For the former case, scattering bars (sub-resolution lines placed adjacent to resolvable lines) or simple linewidth adjustments may be applied to the design. For the latter case, “dog-ear” (serif or hammerhead) features may be attached to the line end in the design. OPC has a cost impact on photomask fabrication, as the addition of OPC features means more spots for defects to manifest themselves. In addition, the data size of the photomask layout goes up exponentially.
The process of training an OPC model using test patterns is called calibration. Often arrays of structures that are simple to generate, such as pitches, line ends, inverse pitches, and inverse line ends are used for calibration. These are representative of many aspects of the chip design, but many of these simple patterns do not capture the complexity of some of designs, for example SRAMS, which are usually two-dimensional (2D), and sub-ground rule patterns.
Consider, for example, a case where it is desired to form a circuit element comprising two parallel lines, each having a specified thickness, with a gap having a certain distance between them. A design of the circuit element may be made, such as on a CAD system, and represents the desired physical implementation (realization of the design, “in silicon”). A lithography mask having an image of the two lines is made, to manufacture the design. The mask image is the same as the design (although it may be magnified, depending on the equipment being used). At extremely small scales, due to optical effects, particularly proximity effects, in the physical implementation of the design, the lines or the gap may become distorted. For example, the gap between the two lines may become larger. This is generally not acceptable.
It is therefore known to modify the mask image, in a controlled manner, so that the resulting physical implementation of the circuit element more accurately represents the original design. For example, box shapes may be added, as extensions to the ends of the two lines, in the mask image, so that the resulting physical realization of the design more accurately represents the intent of the design—namely, two parallel lines, each having a specified length and thickness, with a gap having a certain distance between them. In other words, “what you see” is not “what you get”, and the distortions which occur may advantageously be exploited (incorporated into the modified mask image) so that “what you get” is “what you want”. Generally, there are two ways to implement the desired modifications to the mask image, or “optical proximity correction (OPC), “rule-based” and “model-based”.
In “rule-based” OPC, the approach is to implement a set of design rules, or “formulas”, such as “if this is the condition, then make such correction”. In the aforementioned example of two lines, “if two lines are spaced distance apart, then modify the design to have box shaped extensions at the ends of the lines”.
In “model-based” OPC, a plurality of basic structures are designed, modeled and implemented. In contrast with “rule-based”, “model-based” is more empirical, based on creating and implementing (printing on a wafer) a number of designs, and measuring the results. Using these results, the software is “taught” how to make correlations. By providing a few examples, correlations can be made between the original design and the manufactured wafer (physical implementation). Then, for a new design, a simulation may be performed, to see what happens. The system iteratively goes through this process until a satisfactory result is obtained.
Simple 1- and 2-Dimensional Test Patterns
FIGS. 1C-1F are examples of what may be referred to as “simple” patterns. Simple patterns usually consist of line/space type of structures. Simple patterns are normally used to calibrate an OPC model. Simple patterns are easy to generate, and fairly simple to measure.
For example, in FIG. 1C there is a space “S1” between adjacent (side-by-side) line segments, and that can be considered to be one dimension. If the width “W1” of the line is also included, that can be considered to be a second dimension.
For example, in FIG. 1D there are two areas, separated from one another, each area having two side-by-side line segments. This is generally a one-dimensional pattern.
For example, in FIG. 1E, there are two line segments, end-to-end, with a space “S2” between their tips. Each line segment may also have a length and a width, of interest, making it a “two-dimensional” pattern.
For example, in FIG. 1F, there are a number of pairs of lines segments which are oriented end-to-end, with a space between them. And, one pair of line segments is adjacent (side-by-side) another pair of line segments. This is a 2-dimensional pattern.
FIG. 1C also exhibits what is referred to as “reflectional” symmetry. An image is said to have reflectional symmetry if there is at least one line which splits the image in half so that one side is the mirror image of the other. Reflectional symmetry is also called line symmetry or mirror symmetry because there is a line in the figure where a mirror could be placed, and the figure would look the same. In the examples of FIGS. 1C-1F, each pattern has reflectional symmetry in two orthogonal axes, having what is referred to herein as “orthogonal symmetry”.
For example, in FIG. 1C, the design is symmetrical to the left and right of a vertical dashed line. Also, the design is symmetrical to the top and bottom of a horizontal dashed line. This design has at least two axes (lines) of symmetry. (A design may also be symmetrical about diagonal lines. It is possible to have many lines of reflectional symmetry). Dashed lines representing two axes (horizontal and vertical lines) of symmetry are also shown in FIGS. 1D, 1E and 1F.
Some Exemplary Patent References
U.S. Pat. No. 6,902,854, incorporated by reference herein, discloses method for carrying out a rule-based optical proximity correction with simultaneous scatter bar insertion. Lithographic fabrication of a microelectronic component is performed with the aid of OPC and a scatter bar structure. At least one scatter bar is applied on a mask in addition to a main structure for the purpose of a subsequent imaging of the main structure from the mask onto a substrate by exposure. At least one correction value for the OPC is selected in a particular manner in dependence upon a spacing between two parts of the main structure or spacing between neighboring main structures and the presence of a scatter bar between the two parts of the main structure. The manner in which the correction value is defined is determined by so forming an auxiliary quantity for each scatter bar, that the largest auxiliary quantity that is set is less than the smallest spacing between the parts of the main structure, so that in a program for OPC the presence of a scatter bar between the two parts of the main structure is suggested. In this way, correction values for a rule-based OPC method are flexibly defined even in the presence of scatter bars.
U.S. Pat. No. 6,077,310, incorporated by reference herein, discloses an optical proximity correction system. Pattern data that is an object of correction is divided into an area on which correction is made using correction values that have been obtained in advance for patterns and their respective layouts and an area on which correction is made on the basis of correction values calculated by a simulator. For example, simulation-based correction is made on a gate layer in a memory, while rule-based correction is made on a gate layer in the other area than the memory on the basis of rules for active gate width only. After being subjected to the correction, the areas are combined.
U.S. Pat. No. 6,420,077, incorporated by reference herein, discloses a contact hole model-based optical proximity correction method. The method includes building a contact hole model from the database obtained through a series of test patterns each having a plurality of contact holes of different line widths but identical distance of separation. Line width offsets due to proximity effect are eliminated by referring to the contact hole model.
FIG. 1G is a is a sketch showing the test patterns used by a conventional contact hole model-based optical proximity correction method, such as disclosed in the U.S. Pat. No. 6,420,077 patent.
As shown in FIG. 1G, a square contact hole 102 in test pattern 100 has a line width 104. Distance of separation or pitch from one contact hole 102 to its neighboring contact hole is labeled 106. For example, line width 104 of the square contact hole 102 in test pattern 100 is 0.8 μm and distance of separation between neighboring contact holes is 1.6 μm. Similarly, line width of contact hole 112 in test pattern 110 is 0.84 μm and distance of separation between neighboring contact holes 112 is 1.68 μm. Finally, line width of contact hole 116 in test pattern 114 is 0.88 μm and distance of separation between neighboring contact holes 116 is 1.76 μm.
Using a photomask having the test patterns 100, 110 and 114 thereon, a layer of photoresist is exposed and then developed. Thereafter, line widths of various patterns on the developed photoresist layer are measured. Because of proximity effect, contact hole patterns on the wafer are slightly different from the original test patterns on the photomask. Most probably, the corners of the square holes may be rounded and line width may be smaller. After measuring the actual line widths, a line width versus distance of separation graph may be plotted for both the predicted and the actual values.
Using optical proximity correction based on the model, proper optical mask line widths can supposedly be selected to form the desired line width on the photoresist layer during a contact hole forming process. In practice, the established model can hardly produce the kind of accuracy demanded. This is because proximity effect may vary according to distance of separation, thereby changing the effect on line width. In other words, when the distance of separation is greater than a few times the line width, proximity effect has little influence on line width dimensions. However, as distance of separation is not much different from the line width, proximity effect can affect the ultimate line width dimensions of the contact holes considerably. Hence, a simple distance of separation versus line width relationship can hardly produce the kind of prediction needed for forming contact holes having correct dimensions and position.
Test patterns such as shown in FIG. 1G having contact holes of different line widths but identical distance of separation between neighboring holes may be generated. The ratio between line width and distance of separation between neighboring lines, called “pitch ratio”, is an important design parameter. For example, one test pattern may have a pitch ratio of 0.8:0.8, that is, 1:1. Another test pattern may have a pitch ratio of 0.4:0.8, that is, 1:2. Yet another test pattern may have a pitch ratio of 0.2:0.8, that is, 1:4. In other words, a variety or test patterns may be created, such as in one overall test array using different pitch ratios of the contact holes. Using a photomask having the aforementioned test patterns thereon, the test patterns are transferred to a photoresist layer and then developed. Line widths on the developed photoresist layer are measured. Due to proximity effect, the contact hole patterns on the silicon chip will differ slightly from the original patterns on the photomask. The corners may be rounded and line width may be reduced. By comparing the measured line widths with the original line widths on the photomask, a contact hole model for optical proximity correction is obtained.